In a memory device, such as static random access memory (SRAM) cell, an electrical charge (HIGH) is stored in the memory device to represent a digital “1”, while the absence of such an electrical charge or a relatively low charge (LOW) stored in the device indicates a digital “0”. To increase the ability to write to the memory cell, the power supply voltage for the cell may be reduced during the write cycle. Reducing the power supply voltage for the write cycle is commonly referred to as initiating a VDD collapse.
One technique for implementing bit-cell VDD collapse during a write cycle is to use a pull-down transistor enabled by a write assist signal. Clamping transistors that are coupled between the memory cell supply voltage line and the main power supply voltage maintain VDD at its normal level during normal operations. When the pull-down transistor is enabled prior to a write cycle, the pull-down transistor is in contention with the clamping transistors, but since it is stronger than the clamping transistors, VDD drops.
This scheme creates a large crow-bar current between pull-down and clamp due to the contention-based design. Process Variation (PV) and Bias Temperature Instability Degradation (BTI) can significantly shift up or down the magnitude of the VDD collapse. The up/down shift in collapse can cause bit-cells to either lose their state or prevent a successful write. To combat the variation in the collapse circuitry, columns across the memory are typically shorted together to average out the variation. The need to short columns together prevents this approach from being used in a bit-writable memory design without upsizing the devices to reduce variation, resulting in a significant area increase.
The use of the same reference symbols in different drawings indicates similar or identical items.